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fifo源程序
- fifo源程序,VHDL编写~具有一定的参考价值~-source code of a fifo, writen in VHDL, will be useful to some extent as a reference
uart8.zip
- 使用Libero提供的异步通信IP核实现UART通信,并附带仿真程序。UART设置为1位开始位,8位数据位,1位停止位,无校验。且UART发送自带2级FIFO缓冲,占用FPGA面积很小。,Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to sta
fifo
- FIFO 是一种先进先出数据缓存器,这是一个同步FIFO的VHDL源程序,将FIFO分成几个模块进行设计,最后用顶层文件进行模块化设计。-FIFO is a FIFO buffer, which is a synchronous FIFO in VHDL source code, will be divided into several modules FIFO design, top-level files Finally, the modular design.
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中,前9列为开销字节,它包含了很多重要的信息,本程序为SDH开销的接收处理,查找帧头,分频,勤务话字节E1异步fifo。可拆为三段源代码,不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
program
- 设计实现4bit FIFO, 数据深度为8, 产生满, 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the fi
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
FIFO
- 一个用VHDL源码编写的先进先出(FIFO)缓冲器模块.可以进行FIFO的仿真验证-A source prepared by VHDL FIFO (FIFO) buffer module. Can verify FIFO simulation
75448172geleicounter
- 这是异步fifo的vhdl实现代码,已经在FPGA上通过实践证明,运行状态良好-This is the asynchronous fifo realize the VHDL code has been adopted in the FPGA Practice has proved that running in good condition
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
asynFifo
- 异步fifo在IC设计中,非常重要;是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷(GRAY)变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点,使得整个系统可靠性高和抗干扰能力强,系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构,使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
FIFO
- 512×8bid的FIFO 含工程文件,基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
fifo
- 用VHDL语言写的FIFO代码,可设FIFO的深度-VHDL language with code written in FIFO, FIFO depth can be set up
FIFO
- This code is a FIFO memory vhdl developed in ISE Software
camera_up
- Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备,另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号,然后下采样生成16bit RGB 5:6:5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转,以便适应手持式设备在移动环境
fifo.vhd
- This a FIFO in VHDL Code-This is a FIFO in VHDL Code
fifi
- FIFO code written in VHDL
char_fifo
- character FIFO in VHDL very speed
FIFO
- 设计了一个具有双时钟信号,双复位信号的FIFO,用于FPGA中的数据缓冲,RAM的定义是参数型,可以根据自己的需求,修改此参数,完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this
fifo
- fifo in vhdl file code